The present invention relates to architectures for integrated circuits, and, in particular, to improved methods and apparatuses providing reliable and power conserving, low-voltage operation of memory structures.
Current computer architectures employ various types of memory structures, such as caches and static random access memories (SRAM); scratchpad memories, or high-speed internal memories used for temporary storage of calculations, data, and other work in progress; dynamic random access memories (DRAM); physical register files (PRF); branch target buffers (BTB); translation look-aside buffers (TLB); re-order buffers (ROB); instruction queues (IQ); load/store queues (LSQ); and so forth. These memory structures serve a variety of functions, including providing high speed local storage for processing elements that may help overcome relatively slower access speeds from other memory structures. Successful operation of the these memory structures takes advantage of the ability to predict likely future use of data by the processing element so that data required by the processing element may be pre-stored or retained in the memory structures to be quickly available when that data is needed.
Often multiple hierarchical memory structures are used with the smallest and fastest memory structure operating in coordination with successively larger and slower memory structures. For example, with respect to caches, a smaller and faster Level 1 (L1) cache may typically operate in coordination with successive larger and slower Level 2 (L2) and Level 3 (L3) caches or a Last Level Cache (LLC). Multiple levels of memory structures allow a flexible trade-off between speed of data access and the likelihood that the requested data will be in the memory structure. Memory structures are often managed by memory controllers which determine which portions of the memory should be ejected when new data is required.
With increased circuit density in integrated circuits, power efficiency has become a design priority for high performance and low-power processors and processing elements. The maximum speed of high-performance processors is often limited by problems of power dissipation which may be addressed by improving energy efficiency. For low-power processors, energy efficiency increases the operating time of the processor when operating on as battery power source.
An effective technique to increase processor efficiency is Dynamic Voltage and Frequency Scaling (DVFS) in which the processor voltage and processor clock speed are reduced at times of low processing demand. Reducing the processor voltage and frequency significantly lowers dynamic and static power consumption of transistors.
The minimum voltage (Vmin or VDDMIN) that may be used with DVFS for memory structures is determined by the lowest voltage at which the transistor circuitry of the memory cells of the memory structure may maintain their logical state. Vmin may be reduced by increasing the size of the transistors in the memory cells of the memory structures. This makes the transistors less sensitive to mismatches induced by process variations such as random dopant fluctuations (RDF) and line edge roughness (LER) limits. Increasing the size of these transistors, however, is undesirable because memory structures typically occupy significant physical areas on integrated circuits.
Certain improvements are described in U.S. patent application Ser. No. 13/271,771, titled “Energy Efficient Processor Having Heterogeneous Cache,” the contents of which are hereby incorporated by reference in its entirety. There is a continuing need for greater performance in such memory structures while simultaneous achieving power efficiency.